• Syntax Analysis: Read in HDL files and check for syntax errors. • Library Definition: Provide standard cells and IP Libraries. • Elaboration and Binding: Convert RTL into Boolean structure. State reduction, encoding, register infering.
Bind all leaf cells to provided libraries • Constraint Definition: Define clock frequency and other design constraints • Pre-mapping Optimization: Map to generic cells and perform additional heuristics • Technology Mapping: Map generic logic to technology librar...
원문 링크 : Basic Synthesis Flow
